Flash memories have operating modes that can differ from other types of memories, such as program and erase modes. During these operating modes, various voltage levels may be applied to a wordline associated with a memory cell to cause what is commonly referred to as Fowler-Nordheim (FN) tunneling (such as when a memory cell is being programmed or erased).
A split-gate type memory cell may be advantageous to use in a flash memory as it may provide improved immunity against an over-erasure effect compared to stacked gate memory cells, due to the fact that the gates are isolated from bitlines by portions of transistor selection in those cell regions.
As shown in FIGS. 1A and 1B, a split-gate memory cell can include a floating gate 7 of a polysilicon layer (or a polycide layer) covering parts of a source region 2 and a channel region 4 of a semiconductor substrate 1 by interposing an oxide layer 5 between the channel region 4 and the floating gate 7 having a thickness about 15 nm. The channel region 4 is defined between the source region 2 and a drain region 3 formed in the substrate 1. A control gate 9 of polysilicon is formed over the floating gate 7 and the channel region 4. An oxide layer 8 is between the floating gate 7 and the control gate 9. The oxide layer 8 can be thicker along a vertical distance d2 (about 200 nm) than a lateral distance d1 (about 40 nm). The narrower distance d1 between the side of the floating gate 7 and the control gate 9 can enable electrons to migrate from the floating gate 7 to the control gate 9 by way of a space EFN by FN tunneling.
In a memory cell array, the control gate 9 is coupled to a wordline WL and the source and drain regions, 2 and 3, are connected respectively to a source line SL and a bitline BL. The wordlines and source lines are arranged in rows and the bitlines are arranged in columns. One page in the memory cell array can be associated with a pair of wordlines having, for example, even and odd numbering.
The following Table 1 summarizes voltage bias conditions for conducting the operating modes of programming, erasing, and reading in the split-gate memory cell.
TABLE 1Operation ModeProgrammingErasingReadingWordline (WL)VPGM (11~15 V)VER (11~15 V)VrefBitline (BL)VCC (“1”);VSS1~2 Vprogram inhibitVSS (“0”); programSource Line (SL)10~12 VVSSVSS
As shown in Table 1, when erasing the memory cell (refer to FIG. 1A), the control gate 9 is charged up to the erasing voltage of 11˜15V on the wordline WL while the source and drain regions, 2 and 3, are set to ground (VSS) through the source line SL and the bitline BL. The high-level erasing voltage VER causes electrons (or negative charges) on the floating gate 7 to move into the control gate 9 by the FN tunneling effect, which is sometimes referred to as “forward tunneling”. As a result, a threshold voltage of the memory cell can be decreased depending on the amount of positive charge remaining in the floating gate 7. In this state, the memory cell is conductive in response a reference voltage Vref applied to the wordline WL during the read mode. Such a memory cell is referred to being erased which is indicated as storing data equal to a logical “1”.
Referring to FIG. 1B, programming the split-gate memory cell is accomplished by applying a threshold voltage Vt to the wordline WL, applying 10˜12V to the source line SL and VSS to the bitline BL. The power supply voltage (corresponding to data “1”) can be provided to non-selected bitlines. A threshold voltage level of Vt at the control gate 9 induces a conductive field 4′ in the channel region 4, by which electrons are forced to the floating gate 7 by a hot electron effect while flowing towards the source region 2. The electrons trapped in the floating gate 7 can increase the threshold voltage of the memory cell.
In read mode, the wordline, the bitline, and the source line are charged with the reference voltage Vref, 1˜2V, and VSS, respectively. A read data bit of “1” corresponds to a normally erased memory cell while “0” corresponds to a normally programmed memory cell.
As discussed above, high voltage levels may be needed for programming and erasing operations. In particular, a very high voltage may be needed to provide the FN tunneling effect during the erasing operation. For example, a split-gate memory cell formed using a design rule of 0.35 μm may need a voltage of 12.5V applied to the wordline during the erasing operation which may be less than the breakdown voltage of a high-voltage specific MOS (HVMOS) transistor (which may be about 13V). However, the breakdown voltage of a HVMOS transistor may be reduced as the design rule is reduced. For example, if a design rule of 0.1 μm is used, the breakdown voltage of the HVMOS transistor may be reduced to about 11V despite the fact that a wordline voltage of 11.5V may need to be maintained to ensure that the selected memory cells are properly erased.
The types of the erasing operations may be classified into two groups in accordance with the unit of the flash memory being erased: 1) sector erasure mode and 2) chip erasure mode. A sector may be defined as one page of the flash memory or a plurality of pages. Therefore, the wordline decoders D0˜Dn-1 may all be selected (i.e., having a voltage of 11.5V (VPP) applied to all the wordlines) in the chip erasure mode, or alternatively, selected in the sector erasure mode.
The wordline decoder of FIG. 2 is shown in FIG. 3. The wordline decode is a type a level shifter that transfers VPP to its associated wordline. In the sector erasure mode, if the wordline decoder of FIG. 3 is selected, a NAND gate ND1 outputs a low-level signal in response to high-level address signals A0 and B0. High-voltage NMOS and PMOS transistors, HVN2 and HVP2, become non-conductive and conductive, respectively. A VPP of 11.5V is transferred to a selected wordline WL0 through the PMOS transistor HVP2. A high-voltage PMOS transistor HVP1 is non-conductive to keep a gate of the PMOS transistor HVP2 at a low level since a gate of HVP1 is coupled to the selected wordline WL0 of VPP.
On the other hand, if the wordline decoder of FIG. 3 is not included in the sector selected for erasure (i.e., not selected), the NAND gate ND1 outputs a high-level signal because at least one of the address signals A0 and B0 is set to a low level. The NMOS transistor HVN2 becomes conductive, thereby causing the corresponding wordline WL0 to be set to a low level (i.e., a ground voltage level). As the non-selected wordline WL0 is held to the ground voltage, the PMOS transistor HVP1 becomes conductive and the PMOS transistor HVP2 becomes non-conductive.
To properly erase the memory cells in the selected sector, a source-to-drain voltage of the PMOS transistor HVP2 should be maintained at 11.5V. However, as smaller design rules (e.g., 0.18 μm) are used, narrower gate widths and shorter channel lengths are formed (or a distance between a source and a drain). These reductions in dimensions may make the device more susceptible to leakage current and may cause the breakdown voltage of a high-voltage MOS transistor (e.g., HVP2) to be reduced. For example, as discussed above, if the breakdown voltage of the high-voltage PMOS transistor is 11V, it may be difficult to maintain the source-to-drain voltage of the PMOS transistor HVP2 at the level needed to ensure proper operation (e.g. 11.5V in this example).
On the other hand, the chip erasure mode is conducted with a larger number of wordline decoders than those selected in the sector erasure mode. In this erasure mode, a source-to-drain voltage of the high-voltage PMOS transistor HVP1 should be maintained at the VPP level. However, the PMOS transistor HVP1, which may be smaller than the PMOS transistor HVP2, may not be capable to endure the stress associated such a high source to drain voltage thereby increasing the likelihood of breakdown occurring and a non-selected wordline having VPP is transferred to the non-selected wordline. Applying VPP to non-selected wordlines during an erasure mode may cause malfunctions of erasure operations in the flash memory.